ROME 2018

6th Workshop on Runtime and Operating Systems for the Many-core Era

held in conjunction with IPDPS 2018
May 21 - 25, 2018
Vancouver, British Columbia, Canada


  • May, 1, 2018: Publishing the preliminary program
  • January 31, 2018: Submission deadline extended to Feburayr 12, 2018.
  • October 16, 2017: Workshop website is now open
    Photo by Thom Quine CC BY-SA 2.0, via Wikimedia Commons


Since the beginning of the multicore era, parallel processing has become prevalent across the board. However, in order to continue a performance increase, a further evolutionary step is currently ongoing by moving away from common multicores towards innovative heterogeneous many-core architectures with deep memory hierarchies on a large scale. Such systems, equipped with a significantly higher number of cores per chip than multicores, pose challenges in both hardware and software design. On the hardware side, complex on-chip networks, scratchpads, hybrid memory cubes, non-volatile memory and stacked memory, as well as deep cache-hierarchies and novel cache-coherence strategies currently enrich the respective research areas. However, the ROME workshop focuses on the software side because without complying system software, runtime and operating system support, all these new hardware facilities cannot be exploited. Hence, the challenges in hardware/software co-design are to step beyond traditional approaches and to venture new approaches for runtime, middleware and operating system designs in order to exploit the theoretically available performance of upcoming hardware features as effectively and energy-consciously as possible.

In addition, there is currently a strong trend to converge the areas of cloud and high-performance computing. Classical cloud techniques will soon be used in the area of high-performance computing and vise-versa. Projects and frameworks have already proven the benefits of OS-level virtualization for high-performance computing, whereas high-performance interconnects are able to accelerate cloud applications, too. Moreover, customized operating systems, hypervisors and unikernels are likely to leverage the efficient employment of virtualization on a broad scale.


Authors from all related disciplines are invited to submit unpublished papers regarding their work on many-core related software research regarding operating systems and runtime environments in the area of cloud and high-performance computing. The topics of interest include, but are not limited to:

  • Virtualization techniques (e. g. containers) for high-performance computing
  • System software to converge cloud and high-performance computing
  • Lightweight/specialized operating systems, unikernels and hypervisors
  • New approaches for operating systems on novel (heterogeneous) many-core architectures
  • System software for enabling parallelism at an extreme scale
  • Management, deployment of virtualized environments and orchestration
  • Many-core/multi-node aware runtime support for large-scale applications
  • Bare-metal programming and system software for many-cores
  • Extensions for operating systems and virtualization techniques to support emerging memory technologies
  • System noise analysis and prevention
  • Message-passing interfaces and middleware for many-core systems
  • Heterogeneity-, modularity- and/or hierarchy-aware many-core middleware
  • Software stacks for new concepts of compute acceleration by GPUs, FPGAs and many-core architecture
  • Interfaces for performance and power analysis
  • Runtime support and kernel extensions for power-aware many-core computing

Preliminary Program

The workshop is scheduled on Friday, May 25, 2018.

Keynote and Invited talks

  • 08:40 - 08:45: Welcome speech and announcements
  • 08:45 - 9:30: Keynote by Sang-Hoon Kim, Virginia Tech, USA, Popcorn Linux: System Software for Heterogeneous Hardware
  • 09:30 - 10:00: Invited talk by Karl Fuerlinger: The good, the bad and the ugly: Experiences with developing a PGAS runtime on top of MPI-3

Coffee Break

Session 1: Runtime systems for novel many-core architectures

  • 10:30 - 11:00: Brice Goglin: Memory Footprint of Locality Information on Many-Core Platforms
  • 11:00 - 11:30: Soramichi Akiyama, Takahiro Hirofuchi and Ryousei Takano: Diagnosing Performance Fluctuations of High-throughput Software for Multi-core CPUs

Session 2: Message-passing interfaces and middleware for many-core systems

  • 11:30 - 12:00: Surabhi Jain, Gengbin Zheng, Maria Garzaran, Jim Cownie, Taru Doodi and Terry Wilmarth: Parallelizing MPI using Tasks for Hybrid Programming Models
  • 12:00 - 12:30: Lee Savoie, David Lowenthal, Bronis de Supinski and Kathryn Mohror: A Study of Network Quality of Service in Many-Core MPI Applications

Paper Submission, Paper Style, and Proceedings

Submitted manuscripts may not exceed ten (10) single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. The submitted manuscripts should include author names and affiliations.

The IEEE conference style templates for MS Word and LaTeX provided by IEEE eXpress Conference Publishing are available for download. See the latest versions here.

Upload your submission to our submission server in PDF format. Accepted manuscripts will be included in the IPDPS workshop proceedings.

Important Dates

  • January 30, 2018 February 12, 2018: Submission deadline
  • February 23, 2018 March 5 9, 2018: Notification of acceptance
  • March 18 23, 2018: Workshop camera-ready papers due
  • March 27, 2018: Registration of at least one author per paper
  • May 25, 2018: ROME’18 Workshop

Program Committee

  • Jens Breitbart, Robert Bosch GmbH, Germany
  • Balazs Gerofi, University of Tokyo, Japan
  • Brice Goglin, INRIA, France
  • Carsten Clauss, ParTec Cluster Competence Center GmbH, Germany
  • Alexandra Jimborean, Uppsala University, Sweden
  • Stefan Lankes, RWTH Aachen University, Germany
  • Arthur Maccabe, Oak Ridge National Laboratory, USA
  • Jörg Nolte, BTU Cottbus, Germany
  • Lena Oden, Juelich Supercomputing Centre, Germany
  • Antonio J. Peña, Barcelona Supercomputing Center, Spain
  • Swann Perarnau, Argonne National Laboratory, USA
  • Pablo Reble, Intel Corporation, USA
  • Juan Carlos Saez, Complutense University of Madrid, Spain
  • Bettina Schnor, University of Potsdam, Germany
  • Oliver Sinnen, University of Auckland, New Zealand
  • Christian Terboven, RWTH Aachen University, Germany
  • Josef Weidendorfer, TU München, Germany
  • Carsten Weinhold, TU Dresden, Germany
  • Robert Wisniewski, Intel Corporation, USA

Workshop Organizers