ROME 2017

5th Workshop on Runtime and Operating Systems for the Many-core Era

held in conjunction with Euro-Par 2017
August 28 - September 1, 2017
Santiago de Compostela, Spain



Since the beginning of the multicore era, parallel processing has become prevalent across the board. However, in order to continue a performance increase according to Moore’s Law, a next step needs to be taken: away from common multicores towards innovative many-core architectures. Such systems, equipped with a significant higher amount of cores per chip than multicores, pose challenges in both hardware and software design. On the hardware side, complex on-chip networks, scratchpads, hybrid memory cubes, non-volatile memory and stacked memory, as well as deep cache-hierarchies and novel cache-coherence strategies will enrich the current research areas in the future.

However, the ROME workshop focuses on the software side because without complying system software, runtime and operating system support, all these new hardware facilities cannot be exploited. Hence, the new challenges in hardware/software co-design are to step beyond traditional approaches and to wage new programming models and operating system designs in order to exploit the theoretically available performance of future hardware as effectively and power-aware as possible.


Authors from all related disciplines are invited to submit unpublished papers regarding software for novel many-core hardware architectures. The call for papers especially emphasizes on the challenges and research questions arising from the upcoming generation of heterogeneous and/or massive parallel systems stepping towards a many-core dominated exascale era. The topics of interest include, but are not limited to:

  • New approaches for operating systems on novel many-core architectures
  • Operating system extensions for addressing many-core related issues
  • Many-core aware runtime support for large-scale applications
  • Bare-metal programming and system software for many-cores
  • Dealing with legacy software on novel many-core architectures
  • Virtualization solutions to deal with hardware limitations on many-cores
  • Support for interactivity with and between many-core applications
  • Message-passing interfaces and middleware for many-core systems
  • Heterogeneity- and/or hierarchy-aware many-core middleware
  • Concepts and methods for exploiting deep memory hierarchies
  • Operating system extensions for non-volatile memory support
  • Software stacks for new concepts of compute acceleration on many-cores
  • Interfaces for performance and power analysis on many-core systems
  • Runtime support for power-aware many-core computing


The workshop is scheduled on Monday, August 28, 2017, in room A4.

Session 1


Session 2


Session 3

Paper Submission, Registration, and Publication

Submissions in PDF format should be between 10–12 pages in the Springer LNCS style, which can be downloaded from the Springer Web site The 12 pages limit is a hard limit. It includes everything (text, figures, references). On acceptance of the submission, at least one author is required to register for workshop attendance at Euro-Par 2017 and present the paper in the workshop session.

Upload your submission to our submission server in PDF format.
It must not be simultaneously submitted to the main conference or any other publication outlet.

For the workshop, we will prepare hand-outs with the accepted papers. The revised versions will be published after the conference in the workshop proceedings of Euro-Par 2017, part of the LNCS series of Springer.

Important Dates

  • May 5 May 12, 2017: Submission deadline
  • June 16 June 27, 2017: Notification of acceptance
  • July 7, 2017: Workshop paper (for informal workshop proceedings)
  • August 28, 2017: ROME’17 Workshop
  • October 3, 2017: Workshop camera-ready papers due

Program Committee

  • Jens Breitbart, Robert Bosch GmbH
  • Carsten Clauss, ParTec Cluster Competence Center
  • Florian Kluge, Universität Augsburg
  • Stefan Lankes, RWTH Aachen University
  • Timothy G. Mattson, Intel Labs
  • Jörg Nolte, BTU Cottbus
  • Lena Oden, Jülich Supercomputing Centre
  • Antonio J. Peña, Barcelona Supercomputing Center
  • Swann Perarnau, Argonne National Laboratory
  • Andreas Polze, Hasso-Plattner-Institute
  • Pablo Reble, Intel Corporation
  • Bettina Schnor, University of Potsdam
  • Oliver Sinnen, University of Auckland
  • Christian Terboven, RWTH Aachen University
  • Josef Weidendorfer, TU München
  • Carsten Weinhold, TU Dresden

Workshop Organizers