held in conjunction with Euro-Par 2013, August 26 - August 30, 2013 Aachen, Germany
News
- April 10, 2014: The Euro-Par 2013 Workshop Proceedings are now
online at Springer-Link:
http://link.springer.com/book/10.1007/978-3-642-54420-0
- August 26, 2013: The paper “DYON - Managing a New Scheduling Class
to Improve System Performance in Multicore Systems” is the winner
of the best paper award, which is sponsored by the Intel Labs.
- August 14, 2013: The workshop is scheduled to the lecture room
Generali, which is located in the Super C (see picture). A
detail location plan is published in the program
booklet.
- July 12, 2013: Publishing the preliminary program, the keynote
will be delivered by Tim Mattson, PhD, Intel Corp.
- April 16, 2013: Submission is now open
- March 1, 2013: Workshop website is now open
Photo by ChristosV [CC BY-SA 3.0], via Wikimedia Commons
Background
Since the beginning of the multicore era, parallel processing has
become prevalent across the board. However, in order to continue a
performance increase according to Moore’s Law, a next step needs to be
taken: away from common multicores towards innovative many-core
architectures. Such systems, equipped with a significant higher amount
of cores per chip than multicores, pose challenges in both hardware
and software design. On the hardware side, complex on-chip networks,
scratchpads and memory interfaces as well as cache-hierarchies,
cache-coherence strategies and the building of coherency domains have
to be taken into account.
However, the ROME workshop focuses on the software side because
without complying system software, runtime and operating system
support, all these new hardware facilities cannot be exploited. Hence,
the new challenges in hardware/software co-design are to step beyond
traditional approaches and to wage new programming models and OS
designs in order to exploit the theoretically available performance as
effectively as possible.
Topics
The focus of this workshop stands in the tradition of a successful
series of events hosted by the Many-core Applications Research
Community (MARC). Although this workshop is not considered as a
self-contained MARC symposium, the organizers and several members of
the tentative program committee are part of the MARC community.
Authors from all related disciplines are invited to submit unpublished
papers regarding software for novel many-core hardware architectures.
- Operating system support for novel many-core architectures
- Many-core aware runtime support for large-scale applications
- Virtualization solutions to deal with hardware limitations
- Tools for performance analysis on many-core systems
- Dealing with legacy software on novel many-core architectures
- New approaches for leveraging on-die messaging facilities
- Experiences porting, running, or developing applications
- Traditional and new programming models for novel many-core
hardware
- Bare-metal programming and system software
- Power-aware many-core computing
Program
The workshop takes place in the room Super C - Generali on Monday,
August 26, 2013. It is scheduled as full-day workshop. A detail
location plan is published in the program
booklet.
Session 1 (Chair: Stefan Lankes)
- 09:00 - 09:15: Welcome speech and announcements
- 09:15 - 10:00: Invited talk by Tim Mattson, PhD, Intel Corp,
Computational Software Laboratory,
Predicting the Future in a Rapidly Changing Many-core World
- 10:00 - 10:30: Imran Ashraf, S. Arash Ostadzadeh, Roel Meeuws and
Koen Bertels,
Evaluation Methodology for Data Communication-aware Application
Partitioning
Coffee Break
Session 2 (Scheduling and Load Balancing, Chair: Michael Riepen)
- 11:00 - 11:30: Marcus Völp and Michael Roitzsch,
Elastic Manycores - How to bring the OS back into the scheduling
game?
- 11:30 - 12:00: Ramon Nou, Jacobo Giralt and Toni Cortes,
DYON - Managing a New Scheduling Class to Improve System
Performance in Multicore Systems
- 12:00 - 12:30: Patrick Eitschberger and Jörg Keller,
Energy-efficient and Fault-Tolerant Taskgraph Scheduling for
Manycores and Grids
Lunch Break
Session 3: (Predictable and Reliable Runtimes, Chair: Carsten Trinitis)
- 14:30 - 15:00: Devendra Rai, Lars Schor, Nikolay Stoimenov,
Iuliana Bacivarov and Lothar Thiele,
Designing Applictions with Predictable Runtime Characteristics
for the Baremetal Intel SCC
- 15:00 - 15:30: Lars Schor, Devendra Rai, Hoeseok Yang, Iuliana
Bacivarov and Lothar Thiele,
Reliable and Efficient Execution of Multiple Streaming
Applications on Intel’s SCC Processor
- 15:30 - 16:00: Geoffrey Plouviez, Emmanuelle Encrenaz and Franck
Wajsbür,
A formally verified static hypervisor with hardware support for a
many-core chip
Coffee Break
Session 4: (Scalable Runtimes and Kernel Extensions, Chair: Carsten Clauss)
- 16:30 - 17:00: Aaron Landwehr, Stephane Zuckerman and Guang Gao,
Toward a Self-aware System for Exascale Architectures
- 17:00 - 17:30: Gabor Drescher, Timo Hönig, Sebastian Maier,
Benjamin Oechslein and Wolfgang Schröder-Preikschat
A Scalability-Aware Kernel Executive for Many-Core Operating
Systems
- 17:30 - 18:00: Pablo Reble and Georg Wassen,
Towards Predictability of Operating System supported
Communication for PCIe based Clusters
- 18:00 - 18:10: Closing
Paper Submission, Registration, and Publication
Workshop papers must not exceed ten single-spaced, single-column
pages (LNCS style).
On acceptance of the submission, at least one author is required to
register for workshop attendance at Euro-Par 2013 and present the
paper in the workshop session.
Upload your submission to our submission
server in PDF
format. It must not be simultaneously submitted to the main conference
or any other publication outlet.
For the workshop, we will prepare hand-outs with the revised papers.
These will be published after the conference in the workshop
proceedings of Euro-Par 2013, part of the LNCS series of Springer.
Important Dates
May 31, 2013 June 10, 2013: Submission deadline- July 8, 2013: Notification of acceptance
- August 15, 2013: Camera ready, revised papers due
- August 26, 2013: ROME 2013 Workshop
Committees
- Carsten Clauss, RWTH Aachen University
- Wolfgang Karl, Karlsruhe Institute of Technology
- Stefan Lankes, RWTH Aachen University
- Timothy G. Mattson, Intel Labs
- Jörg Nolte, BTU Cottbus
- Eric Noulard, ONERA
- Andreas Polze, Hasso-Plattner-Institute
- Michael Riepen, Intel Labs
- Bettina Schnor, University of Potsdam
- Oliver Sinnen, University of Auckland
- Carsten Trinitis, TU München
- Theo Ungerer, Universität Augsburg
- Josef Weidendorfer, TU München
Workshop Organizers
- Dr. rer. nat. Stefan Lankes, Dr.-Ing. Carsten Clauss,
Chair for Operating Systems, RWTH Aachen University
rome2013@easychair.org
